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Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack

Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s — says it got there by pulling apart an existing 2D test chip

Synopsys has published silicon results for what it calls the first 3D PCIe 6.0 test chip, a 5nm PHY built into a face-to-face stacked package.

Source: Tom's Hardware · Opens in new tab